Reference Designs

To help you evaluate Power Stamp Alliance member products, we have developed reference design boards designed to accept any PSA power stamp. Please contact a PSA member for more information.

Reference design boards can help to accelerate project development for new server designs and other equipment in a 48 V source environment.


1000A 12-Stamp Reference Design

For the highest-current ASIC chipsets, this 12-stamp reference design offers greater than 1000A peak load, ideal for power-hungry high performance computing (HPC) and supercomputing applications.

600A 6-Stamp ASIC Reference Design Board

For high-current ASIC and/or FPGA chipsets supporting the SVID or AVS protocols, features connections with e-loads and provides sockets to host load modules to test dynamic transient response and enable developers to simulate realistic loading conditions.


Intel® VR13 (Intel® code named Skylake) Reference Design Board

For Intel® VR13 (Intel® code named Skylake) processors


Intel® VR13-HC (Intel® code named Ice Lake) Reference Design Board

For Intel® VR13-HC (Intel® code named Ice Lake) processors


Future Reference Design Boards in Development

The Power Stamp Alliance has a roadmap for future reference design boards for processor architectures used in high performance computing.

Emulation, Testing, Characterization and Validation

LoadSlammer, an associate member of the PSA, can enable even faster deployment times by significantly decreasing selection, implementation, and characterization/ validation testing of the power-stage.

Traditionally, one of the most consuming parts for a systems integrator is evaluating the power delivery system prior to implementing. Understanding the AC characteristics and using that information to drive design decisions in the next stage has been difficult until now.

Using large signal analysis in time and frequency domains gives a significant improvement in system behaviour ahead of implementation.  The real-life data that was previously unavailable can be used in the form of S-parameters to model and optimize performance.

Large-signal impedance analysis is particularly important in the non-linear world of power delivery as virtually all the components in a complex multiphase solution are nonlinear.

Once the power stage has been chosen, it must be characterized/validated and optimized in order to successfully use it with the target device. This process has historically taken considerable time in repeating optimize-and-test cycles.

Characterization and validation of a high current power delivery solution is very time consuming and involves three key stake holders working in tight collaboration. The power supply vendor (PSA) in this case, the digital load vendor and the systems integrator.

A number of studies outline the key resource allocation for getting a fully validated customer ready solution to market.  The largest areas of time consumption are:

  • Generating test vectors
    • Time domain
    • Frequency domain
  • Measurement techniques
  • Sharing and comparing information across multiple stakeholders

PSA members now can provide power-conversion and test-emulation optimized boards to accurately emulate a multitude of applications, and example of which is shown here with sockets for the load-slammers and the position for the power-stamp compliant modules to be mounted.

Application Notes

Contact Cooled Power Stamp Application Study

Parallel Stamp Application Study to Increase Current Rating

Application Guidance for use of Resonant and Non-resonant Stamps